PRSMUX0=DISABLED, INVCLKSYNTH=NO, MMDRSTNOVERRIDEEN=DISABLE, DISCLKSYNTH=ENABLE, PRSMUX1=DISABLED, MMDMANRSTN=RESET
No Description
| LOCKTHRESHOLD | Frequency synthesizer lock threshold |
| PRSMUX0 | PRS output mux 0 selector 0 (DISABLED): PRS output 0 is disabled 1 (INLOCK): Synthesizer is in lock 2 (LOCK_WINDOW): PLL Lock Window, sampled by PFD 3 (FPLL): Divided PLL clock 4 (VCCMP_HI): VCO voltage high detected 5 (VCO_AMPLITUDE_OK): Obsolete. Read returns 1. 6 (VCO_DET_OUT_D): Obsolete. Read returns 0. |
| PRSMUX1 | PRS output mux 1 selector 0 (DISABLED): PRS output 1 is disabled 1 (AUXINLOCK): Obsolete. read returns 0. 2 (REF_IS_LEADING): Disabled. Read returns 0. 3 (FPLL): Divided PLL clock 4 (VCCMP_LOW): VCO voltage low detected 5 (MMD_PRESCALER_RESET_N): MMD prescaler reset, active low 6 (CLK_SYNTH_DIV2): MMD next denom output, corresponding to the delta-sigma clock, divided by 2. |
| DISCLKSYNTH | Disable clk_synth 0 (ENABLE): Enable clk_synth 1 (DISABLE): Disable clk_synth |
| INVCLKSYNTH | Invert clk_synth 0 (NO): Do not invert clk_synth 1 (YES): Invert clk_synth |
| MMDRSTNOVERRIDEEN | Enable MMD reset override 0 (DISABLE): Disable MMD reset override 1 (ENABLE): Enable MMD reset override |
| MMDMANRSTN | Manual MMD reset 0 (RESET): Reset MMD and DSM logic 1 (NORESET): Allow MMD and DSM to run |